1. Field of the Invention
The present invention relates generally to Content Addressable Memories (CAM), also called associative memories.
2. Description of Background Art
A Content Addressable Memory (CAM) has a number of storage locations in which data can be stored. Once data is stored in a location, the location can be addressed using the content (data value) of the location. An input word is compared against a table of allowed values. If there is a match, the location of the matched word is returned. The location is typically used to address a related table and a corresponding word is returned. One application of CAMs is in internet protocol (IP) packet classification where IP addresses and other fields of an internet packet are compared in network switches and routers. In a common form of IP addresses, called a subnet address or an address prefix, definite values are specified for a certain number of bits and the rest of the bits of the address are specified as “x” (don't care) bits. An example for IPv4 addresses is given below:
0110 1100 0111 xxxx xxxx xxxx xxxx xxxx
The bits that are not x (don't care) form the prefix of the address, and the number of prefix bits is called prefix length. A subset of the classification application is to identify the matching prefix that has the longest number of prefix bits. In the more general classification application, several fields must match simultaneously. An example specification for classification is shown in the table of FIG. 19.
Additional fields may be used in the classification, for example 144 bits of specification can be used for Internet Protocol version four (IPv4) classification. In Internet Protocol version six (IPv6), the length of each address field is 128 bits long, and a classification specification can exceed 576 bits. A key characteristic of classification specifications is that each of the fields can have x (don't care) bits. Thus CAMs for classification must permit x (don't care) bits that are not necessarily contiguous. A class of CAMs called ternary CAMs has been introduced to address this need, where there is an extra bit associated with every data bit, called the mask bit.
There are many disadvantages with the conventional ternary CAM structure, however. Since each cell contains two memory cells, and a mask-and-compare circuit, implementation of a table of size w×2n requires w×2n+1 memory elements, and w×2n mask-and-compare circuits. Since every lookup in the table requires the activation of all the cells, power consumption is proportional to w×2n. For large values of n, the cost is considerable, and the power consumption is prohibitive. In addition, since the comparison logic is repeated in every cell, it is expensive and difficult to provide different kinds of comparison, and the typical CAM provides only bit-for-bit compares.
What is needed is a content addressable memory system that a) reduces the number of comparators required, b) uses arrays of pure memory, c) separates comparators from the memory elements, and d) selects specific entries as potential matches before comparing all bits. These changes will result in decreased implementation size, by reducing the number of memory elements and comparators, and a decrease in energy consumption, through a more efficient comparison of data entries.